1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a data output control circuit for controlling data output.
2. Description of the Prior Art
Generally, a Dynamic Random Access Memory (DRAM) is a volatile memory device including a plurality of cells, wherein each of the cells includes one transistor and one capacitor.
A synchronous DRAM has a multibank and a pipelined data path structure, is determined an operation state by commands according to control signals such as /CAS, /RAS and /WE, and operates in synchronization with a system clock.
Such a synchronous DRAM has a Read Access Time tAA which a data transfers from a memory cell to a data output control block in response to a read operation, and a DRAM outputs data in synchronization with an external clock by using a CAS Latency (hereinafter, referred to as CL).
In the meantime, a DRAM generates an Output Enable signal (hereinafter, referred to as OUTEN) in order to output data in synchronization with clocks according to each CL after a read command. An output enable signal generator latches a read command signal, which is inputted in synchronization with an external clock, by a Delay Lock Loop (hereinafter, referred to as DLL) clock (hereinafter, referred to as DLLCLK), thereby generating an OUTEN.
Referring to FIG. 1, a read command signal READ is delayed by a read command delay time tCMD through an internal read command generator 10, and is outputted as an internal read command (hereinafter, referred to as RDCMD). In a DLL-on operation, a DLL 20 negatively delays a clock (hereinafter, referred to as CLK) to generate a DLLCLK. A delay unit 30 generates an inverted DLL clock (hereinafter, referred to as FDLLCLK) obtained by inverting and delaying the phase of the DLLCLK, and outputs the FDLLCLK to an output enable signal generator 40. Accordingly, the output enable signal generator 40 can always perform a domain crossing operation while keeping a half margin of a clock cycle time tCK.
In a DLL-off operation, the DLL 20 positively delays a CLK to generate a DLLCLK. The delay unit 30 generates a FDLLCLK obtained by inverting and delaying the phase of the DLLCLK, and outputs the FDLLCLK to the output enable signal generator 40. However, the output enable signal generator 40 may cause a domain crossing error because it does not ensure a proper domain crossing margin.
A case in which a domain crossing error may occur will be described in more detail with reference to a timing diagram illustrating the domain crossing operation of the output enable signal generator 40.
First, the operation of a data output control circuit in a DLL-on state will be described with reference to FIGS. 2 and 3.
In the DLL-on state, a domain crossing operation can be normally performed even when a high frequency clock is inputted, similarly to a case where a low frequency clock is inputted. That is, the output enable signal generator 40 can latch a RDCMD at the rising edge of a FDLLCLK while keeping a half margin of a clock cycle time tCK.
The normal domain crossing operation is possible because the delay unit 30 compensates for the delay tCMD of the RDCMD and the negative delay of the DLL 20, generates a FDLLCLK obtained by inverting and delaying the phase of a DLLCLK, and ensures a margin.
Next, the operation of the data output control circuit in a DLL-off state will be described with reference to FIGS. 4 and 5.
In the DLL-off state, the domain crossing operation may cause an error when a high frequency clock is inputted, differently from a case where a low frequency clock is inputted. That is, the output enable signal generator 40 may cause a domain crossing error because it does not ensure a proper domain crossing margin when a high frequency clock is inputted, differently from a case where a low frequency clock is inputted.
When a low frequency clock is inputted, it is possible to ensure the enough margin of a pulse width, in which domain crossing can be performed, even when only a positive delay is applied because the DLL 20 is turned off. Accordingly, a domain crossing error does not occur. However, when a high frequency clock is inputted, only a positive delay is applied to a CLK in a case where the DLL 20 has been turned off. Therefore, the delay tCMD of the RDCMD is not compensated for, which results in the occurrence of a cross point at which the rising edges of the RDCMD and the FDLLCLK coincide with each other.
Herein, the cross point denotes the time point at which there is no timing margin between the time point at which the RDCMD is enabled and the rising edge of the FDLLCLK. If the cross point occurs, an error occurs in the process of latching the RDCMD to the FDLLCLK, and the enable timing of an OUTEN becomes improper. As a result, data failure occurs.